Digital signal input buffer circuit having a simple construction and capable of retaining data

ABSTRACT

An input buffer circuit includes a flipflop circuit and receives an input voltage signal and a reference voltage to amplify a difference between the input voltage signal and the reference voltage in response to an activation signal. The input buffer circuit comprises first and second transistors having their sources commonly connected to a first node and their drains coupled to a pair of inputs of the flipflop circuit, respectively. A gate of the first transistor is connected to receive the input voltage signal and a gate of the second transistor is connected to receive the reference voltage. A capacitor is connected at its one end to the first node and at its other end to a second node. There is provided a bias control circuit having an output connected to the second node and operating to respond to a precharge signal so as to bring the second node to a first level and to respond to the activation signal so as to bring the second node to a second level lower than the first level, so that the potential of the first node is consequentially lowered when the input buffer circuit executes the comparison operation in response to the activation signal and a current flowing through the first and second transistors is blocked by the capacitor.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an input buffer for digital signalcircuits, and more specifically to an input buffer for comparing aninput voltage signal with a reference voltage and amplifying the voltagedifference between the output voltage signal and the reference voltage.

2. Description of Related Art

At present, various types of input buffers have been proposed and usedin the field of integrated circuit memories. For a stable and regularoperation, the input buffers should have (1) a function of holding aninput voltage and hence an output signal; (2) a narrow insensible bandor zone in an input level discrimination; and (3) a simple circuitconstruction.

However, some conventional input buffers cannot retain an output data,and therefore, if the input buffer is used, a circuit connected toreceive an output of the input buffer has been required for inputinformation. As a result, the overall construction of the circuitincluding the input buffers had to have an increased number of circuitelements. Furthermore, the conventional input buffers have been requiredto provide a one-shot circuit for elevating the level of an input signaland also capable of receiving a latch signal for introducing an inputsignal to the input buffer.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide aninput buffer which has overcome the above mentioned defects of theconventional input buffer.

Another object of the present invention is to provide an input bufferhaving a data retaining function so that a circuit receiving an outputof the input buffer is not required to have a data holding function.

Still another object of the present invention is to provide an inputbuffer capable of treating a wide voltage range to input signal withoutrequiring a one-shot circuit for elevating a level of an input signal.

A further object of the present invention is to provide an input bufferof simple construction and low power consumption.

The above and other objects of the present invention are achieved inaccordance with the present invention by an input buffer circuit whichincludes a flipflop circuit and which receives an input voltage signaland a reference voltage to amplify a difference between the inputvoltage signal and the reference voltage in response to an activationsignal, comprising first and second transistors having their sourcescommonly connected to a first node and their drains coupled to a pair ofinputs of the flipflop circuit, respectively, a gate of the firsttransistor being connected to receive the input voltage signal and agate of the second transistor being connected to receive the referencevoltage; a capacitor connected at its one end of the first node and atits other end to a second node; and a bias control circuit having anoutput connected to the second node and operating to respond to apercharge signal so as to bring the second node to a first level and torespond to the activation signal so as to bring the second node to asecond level lower than the first level, so that the potential of thefirst node is consequentially lowered when the input buffer circuitexecutes the comparison operation in response to the activation signaland a current flowing through the first and second transistors isblocked by the capacitor.

In a preferred embodiment, the bias control circuit includes a thirdtransistor having a drain connected to a high level voltage and a sourceconnected to the second node, a gate of the third transistor beingconnected to receive the precharge signal, and a source-grounded fourthtransistor having a drain connected to the second node, a gate of thefourth transistor being connected to receive the activation signal.

More specifically, the flipflop circuit fifth and sixth transistorshaving their drains commonly connected to receive the activation signaland their sources connected to third and fourth nodes, respectively,respective gates of the fifth and sixth transistors being connected tofifth and sixth nodes, respectively, a source-grounded seventhtransistor having a drain connected to the third node and a gateconnected to the fourth node, a source-grounded eighth transistor havinga drain connected to the fourth node and a gate connected to the thirdnode, ninth and tenth transistors having their drains connected to ahigh level voltage and their gates connected to receive the perchargesignal, respective sources of the ninth and tenth transistors beingconnected to the fifth and sixth nodes, respectively, andsource-grounded eleventh and twelfth transistors having their drainsconnected to the fifth and sixth nodes, respectively and their gatesconnected to the gates of the seventh and eighth transistors,respectively.

The above and other objects, features and advantages of the presentinvention will be apparent from the following description of preferredembodiments of the invention with reference to the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a conventional input buffer;

FIG. 2 is a more detailed circuit diagram of the conventional inputbuffer shown in FIG. 1;

FIG. 3 is a circuit diagram of one embodiment of the input buffer inaccordance with the present invention; and

FIG. 4 is a more detailed circuit diagram of the input buffer shown inFIG. 3.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 1, there is shown in a circuit diagram of a typicalinput buffer in the prior art. The shown circuit is constructed toreceive an external input voltage V_(IN) and a reference voltage V_(ref)as well as a latch signal φ_(L), a precharge signal φ_(p) and anactivation signal φ_(a) and to generate true and complementary outputsignals φ_(o) and φ_(o). The shown circuit is composed of only N-channelenhancement MOS field effect transistors.

The external input voltage V_(IN) is inputted to a drain of a MOStransistor J₂₃ having a gate connected to receive the latch signalφ_(L), and the reference voltage V_(ref) is inputted to a drain of a MOStransistor J₂₄ having a gate connected to also receive the latch signalφ_(L). A source of the MOS transistor J₂₃ is connected to a node N₂₁,and on the other hand, a source of the MOS transistor J₂₄ is connectedto a node N₂₂. Therefore, if the latch signal φ_(L) of a high level isapplied to the gates of the transistors J₂₃ and J₂₄, the external inputvoltage V_(IN) and the reference voltage V_(ref) are transferred to andheld on the node N₂₁ and N₂₂, respectively.

The node N₂₁ is connected to a gate of MOS transistor J₂₁ having asource grounded and a drain coupled to one input of a differentialamplifier/flipflop circuit 20. on the other hand, the node N₂₂ isconnected to a gate of MOS transistor J₂₂ having a source grounded and adrain coupled to the other input of the differential amplifier/flipflopcircuit 20. The differential amplifier/flipflop circuit 20 operates tocompare two input voltages and to emphasize or amplify a differencebetween the two input voltages.

The node N₂₁ is also connected to one electrode of a capacitor C₂₁ andthe node N₂₂ is also connected to one electrode of capacitor C₂₂. Theother electrodes of these capacitors C₂₁ and C₂₂ are connected to anoutput of a one-shot circuit 30. The one-shot circuit 30 includes a pairof transistors J₂₇ and J₂₈ connected in series between a positive powersupply terminal and ground and connected to receive at their gates theprecharge signal φ_(p) and the activation signal φ_(a), respectively. Aconnection node N₂₄ between the transistors J₂₇ and J₂₈ is connected toa gate of a transistor J₂₅ having a drain connected to receive theactivation signal φ_(a). A source of the transistor J₂₅ is connected toa node N₂₃ which is connected to receive the activation signal φ_(a).The node N₂₃ is connected to the other electrode of the capacitors C₂₁and C₂₂.

As shown in detail in FIG. 2, the differential amplifier/flipflopcircuit 20 can assume one of constructions which are widely used incurrent MOS dynamic random memory integrated circuits with a 5V singlevoltage supply. The circuit 20 includes a pair of transistors J₂₉ andJ₃₀ having their drains commonly connected to receive the activationsignal φ_(a). A source of the transistor J₂₉ is connected to a node N₂₅,which is in turn connected to a drain of a source-grounded transistorJ₃₁, and on the other hand, a source of the transistor J₃₀ is connectedto a node N₂₆, which is in turn connected to a drain of anothersource-grounded transistor J₃₂. A gate of the transistor J₃₁ iscross-connected to the node N₂₆, which is also connected to the drain ofthe transistor J₂₁, and on the other hand, a gate of the transistor J₃₂is cross-connected to the node N₂₅, which is also connected to the drainof the transistor J₂₂.

Furthermore, the differential amplifier/flipflop circuit 20 includes atransistor J₃₃ having its drain to the positive power supply and itsgate connected to receive the precharge signal φ_(p). A source of thetransistor J₃₃ is connected through a node N₂₇ to a gate of thetransistor J₂₉ and a drain of a source-grounded transistor J₃₅ whosegate is connected to the gate of the transistor J₃₁. The connection nodeN₂₇ between the transistors J₃₃ and J₃₅ gives the true output signalφ_(o). On the other hand, there is provided a transistor J₃₄ having itsdrain connected to the positive power supply and its gate connected toreceive the precharge signal φ_(p). A source of the transistor J₃₄ isconnected through a node N₂₈ to a gate of the transistor J₃₀ and a drainof another source-grounded transistor J₃₆ whose gate is connected to thegate of the transistor J₃₂. The connection node N₂₈ between thetransistors J₃₃ and J₃₅ gives the complementary output signal φ_(o).

Incidentally, the reference voltage V_(ref) is given from a referencevoltage generator (not shown) which is installed on the substrate onwhich the above mentioned input buffer is installed. However, thereference voltage generator itself is well known to persons skilled inthe art, and therefore, explanation thereof will be omitted forsimplification of the description.

Now, explanation will be made on operation of the input buffer mentionedabove. First, the precharge signal φ_(p) having a voltage sufficientlyhigher than a threshold voltage V_(T) of the transistors is applied tothe gate of the transistors J₃₃ and J₃₄. Here, a voltage sufficientlyhigher than the threshold voltage V_(T) of the transistors will becalled a "high level". As a result, the transistors J₂₇ , J₃₃ and J₃₄are activated or turned on, so that the nodes N₂₄, N₂₇ and N₂₈ arebrought to a high level. At this time, the activation signal φ_(a) ismaintained at a voltage sufficiently lower than the threshold voltageV_(T) of the transistors (a voltage sufficiently lower than thethreshold voltage V_(T) of the transistors will be called a "low level"hereinafter), and therefore, the nodes N₂₃, N₂₅ and N₂₆ are maintainedat a low level. Thereafter, the precharge signal φ_(p) is brought to alow level.

Then, the latch signal φ_(L) is brought from a low level to a highlevel. Therefore, the external input voltage V_(IN) and the referencevoltage V_(ref) are latched on the nodes N₂₁ and N₂₂, respectively.Thereafter, when the activation signal φ_(a) is brought from the lowlevel to a high level, the nodes N₂₅ and N₂₆ elevate their potentialsthrough the transistors J₂₉ and J₃₀ since the nodes N₂₇ and N₂₈ havebeen maintained at the high level. At the same time, the node N₂₃elevates its potential through the transistor J₂₅ since the node N₂₄ hasbeen maintained at the high level. However, with elapse of time, thepotential of the node N₂₃ is decreased and finally brought to a lowlevel by the action of the transistors J₂₆ and J₂₈ which have beenturned on by the high level activation signal φ_(a). Thus, a one-shotvoltage pulse is generated on the node N₂₃ by the one-shot circuit 30.

As a result, the respective voltages latched on the nodes N₂₁ and N₂₂are elevated by the one-shot voltage appearing on the node N₂₃, by theaction of the capacitors C₂₁ and C₂₂ whose one electrode is connected tothe node N₂₃. Thereafter, the voltages latched on the nodes N₂₁ and N₂₂will decrease with a decrease of the one-shot voltage appearing on thenode N₂₃.

Accordingly, a voltage difference occurs between the nodes N₂₅ and N₂₆by the action of the transistor J₂₁ having its gate connected to thenode N₂₁ and the transistor J₂₂ having its gate connected to the nodeN₂₂. This voltage difference between the nodes N₂₅ and N₂₆ will drive aflipflop formed by the transistors J₃₁ and J₃₂, with the result that oneof the nodes N₂₅ and N₂₆ having a voltage lower than that of the otherwill become further low. Therefore, the transistors J₃₅ and J₃₆ havingtheir gates connected to the nodes N₂₆ and N₂₅, respectively, will lowerone of the nodes N₂₇ and N₂₈. Namely, the true and complementary outputsignals φ_(o) and φ_(o) are determined.

In this circuit, the true output signal φ_(o) is given by an amplifiedsignal in the same phase as that of the input voltage V_(IN) and thecomplementary output signal φ_(o) is given by an amplified signal in aphase inverse to that of the input voltage V_(IN).

The above mentioned input buffer is characterized in that, at an initialstage of the comparison operation triggered by the activation signalφ_(a), the potentials of the nodes N₂₁ and N₂₂ are elevated by theaction of the capacitors C₂₁ and C₂₂ and the one-shot circuit composedof the transistors J₂₅ and J₂₈, so that the operation regions of thetransistors J₂₁ and J₂₂ having their gates connected to the nodes N₂₁and N₂₂, respectively, are effectively or equivalently extended, wherebya stable operation will be attained.

In the above mentioned input buffer, however, when the external inputvoltage V_(IN) is at a high level, the output node N₂₅ will become ahigh level. At this time, since the transistor J₂₂ receiving at its gatethe reference voltage V_(ref) is ceaselessly maintained in an activatedor conducting condition, an electric charge on the one output node N₂₅having the high level will be discharged to the ground through thetransistor J₂₂. As a result, the flipflop circuit cannot retain the highlevel voltage on the node N₂₅. Therefore, if the above mentioned inputbuffer is used, a circuit receiving the output of the input buffer hasbeen required to include a function of holding the information of theinput signal. Accordingly, the circuit including the input buffer hasinevitably needed an increased number of circuit elements.

Furthermore, the above mentioned input buffer has required the one-shotcircuit 30, particularly the transistors J₂₅ and J₂₆ for generating andsupplying a one-shot voltage pulse to the nodes N₂₁ and N₂₂, as well asthe transfer gate transistors J₂₃ and J₂₄ for introducing the inputvoltage and the reference voltage to the nodes N₂₁ and N₂₂,respectively, and the application of the latch signal φ_(L) to therespective gates of the transfer transistors. In addition, a pair ofcapacitors C₂₁ and C₂₂ have been required. Therefore, the overallcircuit or system including the above mentioned input buffer is of largescale.

Referring to FIG. 3, there is shown in a circuit diagram of oneembodiment of the input buffer in accordance with the present invention.The shown input buffer receives an external input voltage V_(IN) and areference voltage V_(ref) as well as precharge signal φ_(p) and anactivation signal φ_(a), similar to the conventional input buffer shownin FIG. 1, but does not require a latch signal φ_(L), as does theconventional input buffer. In addition, the shown input buffer generatestrue and complementary output signals φ_(o) and φ_(o), similar to theconventional input buffer shown in FIG. 1. Furthermore, the circuitshown in FIG. 3 is composed of only N-channel enhancement MOS fieldeffect transistors, similar to the conventional input buffer shown inFIG. 1.

The input buffer shown in FIG. 3 includes one pair of transistors J₁ andJ₂ having their gates connected to receive the external input voltageV_(IN) and the reference voltage V_(ref), respectively. Thesetransistors are connected at their drains to a pair of inputs of adifferential amplifier/flipflop circuit 10, respectively, and have theirsources commonly connected to a node N₁. The node N₁ is connectedthrough a capacitor C to another node N₂, which is in turn connected toa source of a transistor J₃ and a drain of a transistor J₄. TransistorsJ₃ and J₄ form a bias control circuit for controlling the bias potentialat node N₂. The transistor J₃ has its drain connected to a positivevoltage supply and its gate connected to rfeceive the precharge signalφ_(p). On the other hand, the transistor J₄ has its source grounded andits gate connected to receive the activation signal φ_(a). Furthermore,the differential amplifier/flipflop circuit 10 receives the prechargesignal φ_(p) and the activation signal φ_(a), and generates the true andcomplementary output signals φ_(o) and φ_(o) on the basis of a voltagedifference between the external input voltage V_(IN) and the referencevoltage V_(ref).

In the input buffer shown in FIG. 3, a potential change on the node N₂caused by the transistors J₃ and J₄ will be transferred to the node N₁by an AC voltage transfer function of the capacitor C. As a result, fora period of a high level activation signal, the potential on the node N₁will be made further lower than the (low) level at the time of a highlevel precharge signal. Accordingly, the operation range of thetransistors J₁ and J₂ will be equivalently enlarged. Thus, thedifferential amplifier/flipflop circuit 10 will stably operate, and canhold therein the information of the input voltage signal V_(IN).

Turning to FIG. 4, there is shown a circuit diagram of the input buffershown in FIG. 3 but illustrating one example of the differentialamplifier/flipflop circuit 10. The shown differential amplifier/flipflopcircuit 10 has substantially the same construction as that of thedifferential amplifier/flipflop circuit 20 shown in FIG. 2. Namely, thedifferential amplifier/flipflop circuit 10 includes a pair oftransistors J₆ and J₇ having their drains commonly connected to receivethe activation signal φ_(a), respectively. A source of the transistor J₆is connected to a node N₃, which is turn connected to a drain of asource-grounded transistor J₈, and on the other hand, a gate of thetransistor J₈ is connected to a node N₄, which is in turn connected to adrain of another source-grounded transistor J₈ is cross-connected to thenode N₄, which is also connected to the drain of the transistor J₁, andon the other hand, a gate of the transistor J₉ is cross-connected to thenode N₃, which is also connected to the drain of the transistor J₂.Furthermore, the differential amplifier-flipflop circuit 10 includes atransistor J₁₀ having its drain connected to the ppositive power supplyand its gate connected to receive the precharge signal φ_(p). A sourceof the transistor J₁₀ is connected through a node N₅ to a gate of thetransistor J₆ and a drain of a source-grounded transistor J₁₂, whosegate is connected to the gate of the transistor J₈. The connection nodeN₅ between the transistors J₁₀ and J₁₂ gives the true output signalφ_(o). On the other hand, there is provided a transistor J₁₁ having itsdrain connected to the positive power supply and its gate connected toreceive the precharge signal φ_(p). A source of the transistor J₁₁ isconnected through a node N₆ to a gate of the transistor J₇ and a drainof a another source-grounded transistor J₁₃, whose gate is connected tothe gate of the transistor J₉. The connection node N₆ between thetransistors J₁₁ and J₁₃ gives the complementary output signal φ_(o).

Now, explanation will be made on operation of the input buffer shown inFIG. 4. First, the precharge signal φ_(p) is brought to a high level.Therefore, the transistors J₃, J₁₀ and J₁₁ receiving at their gates theprecharge signal φ_(p) are turned on so that the nodes N₂, N₅ and N₆ arebrought to a high level. At this time, the activation signal φ_(a) ismaintained at a low level, the nodes N₁, N₃ and N₄ are maintained at alow level. Thereafter, the precharge signal φ_(p) is brought to a lowlevel.

Then, when the activation signal φ_(a) is brought from the low level toa high level, the nodes N₃ and N₄ elevate their potentials through thetransistors J₆ and J₇ since the nodes N₅ and N₆ have been maintained atthe high level. At the same time, the node N₂ changes its potential fromthe high level to the low level as the result of the turning-on of thetransistor J₄. Accordingly, the potential of the node N₁ is furtherlowered through the capacitor C (namely, by an AC mode potentialtransfer function of the capacitor) to a level which is lower than thatwhen the precharge signal φ_(p) was brought to the high level.Therefore, the potentials of the nodes N₃ and N₄ will change inaccordance with the gate voltages of the transistors J₁ and J₂,respectively. Thus, a voltage difference corresponding to the externalinput signal V_(IN) will appear between the nodes N₃ and N₄, so that aflipflop formed by the transistors J₈ and J₉ will amplify the voltagedifference, with the result that one of the nodes N₃ and N₄ is broughtto a low level.

Therefore, the transistors J₁₂ and J₁₃ having their gates connected tothe nodes N₄ and N₃, respectively, will lower one of the nodes N₅ andN₆. Namely, the true and complementary output signals φ_(o) and φ_(o)are determined. The true output signal φ_(o) is in the same phase asthat of the input voltage V_(IN) and the complementary output signalφ_(o) is in a phase inverse to that of the input voltage V_(IN) .

In the above mentioned operation of the input buffer, the electriccharge on the nodes N₃ and N₄ is discharged by only an amount whichcharges the capacitor C through the transistors J₁ and J₂. In any case,a DC current will not flow through the nodes N₃ and N₄. Therefore, thedifferential amplifier/flipflop circuit 10 can hold therein theinformation of the input signal, and hence the output signal.

As seen from the above description, the above mentioned input bufferoperates to lower the potentials of the sources of the transistors J₁and J₂ to a level lower than that of the sources of the transistors J₁and J₂ at an initial stage of the operation of the input buffer, by theaction of the capcitor C and the transistors J₃ and J₄, so that thedifferential amplifier/flipflop circuit 10 is realized to stably operateand can hold therein the information of the input signal.

As will be apparent from the above description, the input buffer inaccordance with the present invention is characterized in that acapacitor is connected at its one end commonly to respective sources ofa first pair of transistors which are connected at their gates toreceive an external input voltage and a reference voltage, respectivelyand in that a potential of the other end of the capacitor is controlledby a second pair of series-connected transistors which receive aprecharge signal and an activation signal, respectively. The first pairof transistors is connected at its drains to a pair of inputs of adifferential amplifier/flipflop circuit. Therefore, a current flowingthrough the first pair of transistors will be blocked by the capacitor,and therefore, the differential amplifier/flipflop circuit can retaintherein information of a signal applied through the first pair oftransistors. Accordingly, a circuit receiving the output of the inputbuffer is not required to have a circuit for retaining information ofthe signal outputted from the input buffer. In other words, the overallconstruction of a system or circuit including the input buffer willbecome more simple.

Furthermore, the input buffer in accordance with the present inventionis characterized in that a latch circuit is not required for holding anexternal input signal, and therefore, the circuit is low in electriccurrent consumption.

In addition, the first pair of transistors, connected at its gates toreceive the external input voltage and the reference voltage,respectively, can have an operation region equivalently enlarged by theaction of the potential of the other end of the capacitor controlled bythe second pair of series-connected transistors. Therefore, thedifferential amplifier/flipflop circuit can realize a stable operation.

The above mentioned embodiment of the input buffer circuit is composedof only enhancement type N-channel MOS transistors. However, it would beapparent to persons skilled in the art that the input buffer circuit inaccordance with the present invention can be composed of P-channel MOStransistors or bipolar transistors, and such a circuit will operatesimilar to that of the above mentioned embodiment.

The invention has thus been shown and described with reference to thespecific embodiments. However, it should be noted that the presentinvention is in no way limited to the details of the illustratedstructures but changes and modifications may be made within the scope ofthe appended claims.

What is claimed is:
 1. An input buffer circuit which includes a flipflopcircuit and which receives an input voltage signal and a referencevoltage to amplify a difference between the input voltage signal and thereference voltage in response to an activation signal, comprising firstand second transistors having their sources commonly connected to afirst node and their drains coupled to a pair of inputs of the flipflopcircuit, respectively, a gate of the first transistor being connected toreceive the input voltage signal and a gate of the second transistorbeing connected to receive the reference voltage; a capacitor connectedas its one end to the first node and at its other end to a second node;and a bias control circuit having an output connected to the second nodeand operating to respond to a precharge signal so as to bring the secondnode to a first level and to respond to the activation signal so as tobring the second node to a second level lower than the first level, sothat the potential of the first node is consequentially lowered when theinput buffer circuit executes the comparison operation in response tothe activation signal and a current flowing through the first and secondtransistors is blocked by the capacitor.
 2. An input buffer circuitclaimed in claim 1 wherein the bias control circuit includes a thirdtransistor having a drain connected to a high level voltage and a sourceconnected to the second node, a gate of the third transistor beingconnected to receive the precharge signal, and a source-grounded fourthtransistor having a drain connected to the second node, a gate of thefourth transistor being connected to receive the activation signal. 3.An input buffer circuit claimed in claim 2 wherein the flipflop circuitincludes fifth and sixth transistors having their drains commonlyconnected to receive the activation signal and their sources connectedto third and fourth nodes, respectively, gates of the fifth and sixthtransistors being connected to fifth and sixth nodes, respectively, asource-grounded seventh transistor having a drain connected to the thirdnode and a gate connected to the fourth node, a source-grounded eighthtransistor having a drain connected to the fourth node and a gateconnected to the third node, ninth and tenth transistors having theirdrains connected to a high level voltage and their gates connected toreceive the precharge signal, respective sources of the ninth and tenthtransistors being connected to the fifth and sixth nodes, respectively,and source-grounded eleventh and twelfth transistors having their drainsconnected to the fifth and sixth nodes, respectively and their gatesconnected to the gates of the seventh and eighth transistors,respectively.
 4. An input buffer circuit which includes a differentialcircuit and which receives an input voltage signal and a referencevoltage to amplify a difference between the input voltage signal and thereference voltage in response to an activation signal, comprising:firstand second transistors each having a main current path and a controlelectrode for controlling a current flowing through the main currentpath respective one ends of the main current paths of the first andsecond transistors being connected commonly to a first node, respectiveother ends of the main current paths of the first and second transistorsbeing coupled to a pair of inputs of the differential circuit,respectively, the control electrode of the first transistor beingconnected to receive the input voltage signal and control electrode ofthe second transistor being connected to receive the reference voltage;a capacitor connected at its one end of the first node and at its otherend to a second node; and a bias control circuit having an outputconnected to the second node and operating to respond to a prechargesignal so as to bring the second node to a first level and to respond tothe activation signal so as to bring the second node to a second levellower than the first level, so that the potential of the first node isconsequentially lowered when the input buffer circuit executes thecomparison operation in response to the activation signal and a currentflowing through the first and second transistors is blocked by thecapacitor.
 5. An input buffer circuit claimed in claim 4 wherein thebias control circuit includes third and fourth transistors each having amain current path and a control electrode for controlling a currentflowing through the main current path one end of the main current pathof the third transistor being connected to a high level voltage, theother end of the main current path of the third transistor beingconnected to the second node, the control electrode of the thirdtransistor being connected to receive the precharge signal, and one endof the main current path of the fourth transistor being connected to thesecond node, the other end of the main current path of the fourthtransistor being grounded, and the control electrode of the fourthtransistor being connected to receive the activation signal.